Technical Program Area

Area 8: Design and Implementation of Signal Processing Systems(DISPS)

Session: DISPS-L1
Time: 15:30 - 17:30, Wednesday, June 7, 2000
Location: Mercury-Millennium Center
Title: DSP SILICON SYSTEMS
Chair: Takao Nishitani, NEC Corporation, Japan
1. Paper ID: 83 SMART ANTENNA RECEIVER FOR GSM/DCS SYSTEM BASED ON SINGLE CHIP SOLUTION, U. Girola, A. Picciriello, D. Vincenzoni, ITALTEL S.p.A., Italy.
2. Paper ID: 933 RISC + SIMD = DSP?, H. Shi, Infineon Technologies, USA.
3. Paper ID: 3856 A LOW COST DYNAMIC VOCABULARY SPEECH RECOGNIZER ON A GPP-DSP SYSTEM, Y.-H. Kao, Texas Instruments, USA.
4. Paper ID: 2191 DSP IMPLEMENTATION ISSUES FOR UMTS-CHANNEL CODING, U. Walther, Dresden University of Technology, Germany.
5. Paper ID: 4126 A COMPACT LOW-POWER DECIMATION FILTER FOR SIGMA DELTA MODULATOR, S.-F. Li, J. Wetherrel, University of California, Berkeley, USA.
6. Paper ID: 704 HIGH LEVEL PROGRAMMING FOR REAL TIME FPGA BASED VIDEO PROCESSING, K. Benkrid, D. Crookes, The Queen's University of Belfast, United Kingdom, J. Smith, VisiCom Laboratories, USA, A. Benkrid, The Queen's University of Belfast, United Kingdom.
7. Paper ID: 1183 CUSTOM COMPUTING IMPLEMENTATION OF TWO-STEP BLOCK MATCHING SEARCH ALGORITHM, V. Chung, La Trobe University, Australia, M. Wong, University of New South Wales, Australia, N. Bergmann, Queensland University of Technology, Australia.
8. Paper ID: 3553 LOCALIZED WATERMARKING: METHODOLOGY AND APPLICATION TO TEMPLATE MAPPING, D. Kirovski, M. Potkonjak, University of California, Los Angeles, USA.

Session: DISPS-L2
Time: 09:00 - 12:00, Thursday, June 8, 2000
Location: Altin Kubbe-Hilton Hotel
Title: LOW ENERGY DSP SYSTEMS/DSP DESIGN
Chair: Wanda Gass, Texas Instruments, USA
1. Paper ID: 3518 VARIABLE VOLTAGE TASK SCHEDULING FOR MINIMIZING ENERGY OR MINIMIZING POWER, A. Manzak, C. Chakrabarti, Arizona State University, USA.
2. Paper ID: 3903 LOW-POWER DIGITAL FILTERING VIA SOFT DSP, R. Hegde, N. Shanbhag, University of Illinois, USA.
3. Paper ID: 2682 A NOVEL MULTIPLY MULTIPLE ACCUMULATOR COMPONENT FOR LOW POWER PDSP DESIGN, V. Sundararajan, K. Parhi, University of Minnesota, USA.
4. Paper ID: 4081 PEAK CURRENT ESTIMATION FOR DIGITAL FILTERS, S. Bobba, I. Hajj, University of Illinois at Urbana-Champaign, USA.
5. Paper ID: 4054 AN ORDER BASED SEGMENTATION ALGORITHM FOR LOW POWER IMPLEMENTATION OF DIGITAL FILTERS, A. Erdogan, T. Arslan, Edinburgh University, United Kingdom.
6. Paper ID: 1970 A HIGH PERFORMANCE CARRY-SAVE TO SIGNED-DIGIT RECODER FOR FUSED ADDITION-MULTIPLICATION, W.-C. Yeh, C.-W. Jen, National Chiao Tung University, Taiwan.
7. Paper ID: 3957 RAPID PROTOTYPING FOR MIXED ARCHITECTURES, V. Fresse, O. Deforges, M. Assouil, INSA Rennes, France.
8. Paper ID: 3260 LINEAR DISTANCES AS BRANCH METRICS FOR VITERBI DECODING OF TRELLIS CODES, H.-L. Lou, Lucent Technologies, USA.
9. Paper ID: 2204 DSP CORE VERIFICATION USING AUTOMATIC TEST CASE GENERATION, T. Glokler, S. Bitterlich, H. Meyr, Institute for Integrated Signal Processing Systems, Germany.
10. Paper ID: 3960 REDUCING HARDWARE REQUIRED IN FIR FILTER DESIGN, M. Soderstrand, L. Johnson, H. Arichanthiran, M. Hoque, R. Elangovan, Oklahoma State University, USA.

Session: DISPS-P1
Time: 09:00 - 12:00, Wednesday, June 7, 2000
Location: Ballroom-Hilton Hotel (P6)
Title: IMPLEMENTATION OF FILTERS AND TRANSFORMS
Chair: Teresa Meng, Stanford University, USA
1. Paper ID: 3310 EXPLICIT COOK-TOOM ALGORITHM FOR LINEAR CONVOLUTION, Y. Wang, Florida Atlantic University, USA, K. Parhi, University of Minnesota, USA.
2. Paper ID: 3039 HIERARCHICAL PIPELINING AND FOLDING OF QRD-RLS ADAPTIVE FILTERS, L. Gao, K. Parhi, University of Minnesota, USA.
3. Paper ID: 3671 WAVELET PACKET TRANSFORMS FOR SYSTEM-ON-CHIP APPLICATIONS, S. Masud, J. McCanny, The Queen's University of Belfast, United Kingdom.
4. Paper ID: 4125 AN ADAPTIVE-SEARCH RESIDUAL VECTOR QUANTIZER FOR AIRBORNE RECONNAISSANCE, S. Budge, C. Peel, Utah State University, USA.
5. Paper ID: 595 MINIMALLY REDUNDANT PARALLEL IMPLEMENTATION OF DIGITAL FILTERS AND VECTOR SCALING, K. Muhammad, Texas Instruments, USA, K. Roy, Purdue University, USA.
6. Paper ID: 1148 LOW-COST UNIFIED ARCHITECTURES FOR COMPUTATION OF DISCRETE TRIGONOMETRIC TRANSFORMS, S.-F. Hsiao, W.-R. Shiue, National Sun Yat-Sen University, Taiwan.
7. Paper ID: 3012 PIPELINE ARCHITECTURE FOR 8X8 DISCRETE COSINE TRANSFORM, J. Takala, J. Nikara, Tampere University of Technology, Finland, D. Akopian, Nokia Mobile Phones, Inc., Finland, J. Astola, J. Saarinen, Tampere University of Technology, Finland.
8. Paper ID: 4147 TIME-SHARING ARCHITECTURES FOR FIR FILTER STRUCTURES, S. Meier, M. Schöbinger, Infineon Technologies, Germany.
9. Paper ID: 715 FAULT-TOLERANT DISCRETE-TIME LINEAR TIME-INVARIANT FILTERS, C. Hadjicostis, University of Illinois at Urbana-Champaign, USA.
10. Paper ID: 2197 FFT-BASED FAST POLYNOMIAL ROOTING, L. Hoteit, Schlumberger Cambridge Research, United Kingdom.
11. Paper ID: 2157 FAST IMPLEMENTATION TECHNIQUE FOR IMPROVING THROUGHPUT OF RLS ADAPTIVE FILTERS, K. Nishikawa, H. Kiya, Tokyo Metropolitan University, Japan.
12. Paper ID: 3505 COST EFFECTIVE DIGITAL FILTER DESIGN FOR CONCURRENT TEST, I. Bayraktaroglu, A. Orailoglu, University of California, San Diego, USA.
13. Paper ID: 1333 PASS LOGIC CIRCUITS WITH REDUCED SWITCHING ACTIVITY FOR LOW POWER DSP PROCESSORS, D. Radhakrishnan, Nanyang Technological University, Singapore.
14. Paper ID: 3764 A GENERIC SYSTOLIC PROCESSOR FOR REAL TIME GRAYSCALE MORPHOLOGY, O. Deforges, INSA Rennes, France, N. Normand, IRESTE, France.
15. Paper ID: 4058 PARALLEL IMPLEMENTATION OF MULTIFILTERS, N. Damera-Venkata, B. Evans, The University of Texas at Austin, USA.
16. Paper ID: 4078 A COMPACT MODULAR ARCHITECTURE FOR HIGH-SPEED BINARY SORTING, I. Hatirnaz, F. Gurkaynak, Y. Leblebici, Worcester Polytechnic Institute, USA.
17. Paper ID: 327 A NEW RADIX-6 FFT ALGORITHM SUITABLE FOR MULTIPLY-ADD INSTRUCTION, D. Takahashi, The University of Tokyo, Japan.
18. Paper ID: 3343 IN SEARCH OF THE OPTIMAL WALSH-HADAMARD TRANSFORM, J. Johnson, Drexel University, USA, M. Pueschel, Carnegie Mellon University, USA.
19. Paper ID: 113 GENERALIZATION OF THE CYCLIC CONVOLUTION SYSTEM AND ITS APPLICATIONS, H. Murakami, Kanazawa Institute of Technology, Japan.
20. Paper ID: 2733 A NEW APPROACH TO MODEL COMMUNICATION FOR MAPPING AND SCHEDULING DSP-APPLICATIONS, C. Mathis, B. Rinner, M. Schmid, R. Schneider, R. Weiss, Technical University Graz, Austria.

Session: DISPS-P2
Time: 15:15 - 17:00, Thursday, June 8, 2000
Location: Convention Center Upper Hall (P1)
Title: ALGORITHMS, ARCHITECTURES AND DESIGN METHODOLOGIES
Chair: Ed Deprettere, Technical University of Delft, Netherlands
1. Paper ID: 1752 A FAST OFDM-CDMA USER DEMULTIPLEXING ARCHITECTURE, P. Marti-Puig, University of Vic, Spain, J. Sala-Alvarez, Universidad Politecnica de Cataluña, Spain.
2. Paper ID: 1948 PARAMETERIZED DATAFLOW MODELING OF DSP SYSTEMS, B. Bhattacharya, S. Bhattacharyya, University of Maryland, College Park, USA.
3. Paper ID: 3729 TRACE BACK TECHNIQUES ADAPTED TO THE SURVIVING MEMORY MANAGEMENT IN THE M ALGORITHM, E. Boutillon, L. Gonzalez, Ecole Nationale Superieure des Telecommunications, France.
4. Paper ID: 3116 DECODING METRICS AND THEIR APPLICATIONS IN VLSI TURBO DECODERS, Z. Wang, K. Parhi, University of Minnesota, USA.
5. Paper ID: 1202 AN ARCHITECTURAL ENHANCEMENT FOR REDUCING BACKGROUND COMPUTATION IN ADAPTIVE MOTION ESTIMATION, V. Moshnyaga, K. Nakasima, Fukuoka University, Japan.
6. Paper ID: 3727 SIMPLIFIED PATH METRIC UPDATING IN THE M ALGORITHM FOR VLSI IMPLEMENTATION, L. Gonzalez, E. Boutillon, Ecole Nationale Superieure des Telecommunications, France.
7. Paper ID: 1869 A DECISION-DIRECTED CONSTANT MODULUS ALGORITHM FOR HIGHER-ORDER SOURCE CONSTELLATIONS, T. Endres, S. Hulyalkar, C. Strolle, T. Schaffer, R. Casas, NxtWave Communications, USA.
8. Paper ID: 1645 RECONFIGURABLE COMPUTING IMPLEMENTATION OF BINARY MORPHOLOGICAL OPERATORS USING 4-, 6- AND 8- CONNECTIVITY, H. Talu, E. Igci, M. Tekin, H. Sevtekin, B. Genc, M. Heywood, Dokuz Eylüi University, Turkey.
9. Paper ID: 2615 PARALLEL VITERBI ALGORITHM FOR A VLIW DSP, S. Khan, National University of Sciences and Technology, Pakistan, M. Saqib, S. Ahmed, Communications Enabling Technologies, USA.
10. Paper ID: 1925 COMPUTING RESOURCE BOUNDS USING INCLUSION SCHEDULING, C. Chantrapornchai, Silapkorn University, Thailand, S. Tongsima, National Electronics and Computer Technology Center, Thailand.

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